The present invention relates to a semiconductor memory device and a control method for the same.
With the progress towards finer design rules in CMOS process, variation in transistor characteristics is increasing. Particularly, because finer transistors are used for memory cells in SRAM (Static Random Access Memory), the effect of variation is significant. The increase in the variation of the characteristics of transistors constituting memory cells leads to a decrease in the yield of SRAM and a decrease in the operating speed of SRAM.
To address the above problem, it is effective to reduce the offset voltage of a sense amplifier, which is a component of SRAM. This is because reduction of the offset voltage allows reduction of bit line delay, which is a main cause of the decrease in the operating speed of SRAM. Note that the bit line delay is the time required until a potential difference of a bit line pair exceeds the offset voltage of a sense amplifier after a word line is activated in the case of reading data from a data read target memory cell.
A technique to reduce the offset voltage of a sense amplifier is disclosed in Japanese Unexamined Patent Application Publication No. 2010-73249. As shown in FIG. 12, the sense amplifier disclosed in Japanese Unexamined Patent Application Publication No. 2010-73249 includes a differential amplifier circuit 200 that generates an amplification signal according to a difference between a first input signal voltage BT and a second input signal voltage BB, an output circuit 201 that is connected to the differential amplifier circuit 200 and receives the amplification signal, and a load 202 that is connected to the differential amplifier circuit 200.
The differential amplifier circuit 200 includes a first output node N10 that supplies the amplification signal to the output circuit 201 and a second output node N20 that is placed at the position symmetric to the first output node N10 and connected to the load 202. The output circuit 201 has an output terminal that outputs an output signal generated based on the amplification signal.
Further, the load 202 is configured to switch between a first capacitance that makes an offset voltage at the output terminal a first voltage and a second capacitance that makes the offset voltage a second voltage. Thus, a systematic offset (center value) goes more negative than 0 mV when an offset adjustment signal adj is Disable, and the systematic offset goes more positive than 0 mV when the offset adjustment signal adj is Enable.
In a sense amplifier in which an offset voltage is negative than the systematic offset due to random variation, the offset voltage is brought back to the positive by setting the offset adjustment signal adj to Enable. The range of variation of the offset voltage is thereby reduced. By performing the same processing on each sense amplifier, the range of distribution of variation of the offset voltage is reduced as shown in FIG. 13.
As described above, in the technique disclosed in Japanese Unexamined Patent Application Publication No. 2010-73249, it is adjusted so that the systematic offset goes more negative than 0 mV when the offset adjustment signal adj is Disable. For example, it is adjusted so that the systematic offset is more negative than 0 mV by the amount of 30 mV when the offset adjustment signal adj is Disable. Therefore, the offset voltage of a sense amplifier whose offset voltage has been low before adjustment is also adjusted to be shifted to the negative by the amount of 30 mV. Thus, the technique disclosed in Japanese Unexamined Patent Application Publication No. 2010-73249 has a problem that the offset voltage of a sense amplifier with a low offset voltage increases.
A solution to the above problem is disclosed in Japanese Unexamined Patent Application Publication No. 2007-280537. As shown in FIGS. 14 and 15, a semiconductor integrated circuit device disclosed in Japanese Unexamined Patent Application Publication No. 2007-280537 includes two bit lines BL and BLB, input nodes IN1 and IN2, sense nodes S and SB that transmit amplification signals according to a difference between input signals input to the bit lines BL and BLB or the input nodes IN1 and IN2, an output node OUTB that outputs an amplification signal, current adjustment gates TG1 and TG2 that adjust the amount of current flowing through the sense nodes S and SB, latch circuits LC1 and LC2 that control the current adjustment gates, signal lines SL1 and SL2 that transmit a power supply voltage Vdd and a comparative voltage (Vdd−Voff), and switching elements SW1 and SW2 that are placed between the input nodes IN1 and IN2 and the signal lines SL1 and SL2.
In the case where the amplification signal is an inversion signal of a signal corresponding to a threshold voltage Voff when the power supply voltage Vdd and the comparative voltage (Vdd−Voff) are input to the input nodes IN1 and IN2, the latch circuits switch the current adjustment gates. The distribution of the offset voltage is thereby improved as shown in FIG. 16.
In the technique disclosed in Japanese Unexamined Patent Application Publication No. 2007-280537, only the sense amplifier SA with the offset voltage of the threshold voltage Voff or higher is selectively trimmed, which is different from the case of the technique disclosed in Japanese Unexamined Patent Application Publication No. 2010-73249.